HyperTransportTM technology has revolutionized microprocessor core interconnect. It serves as the central interconnect technology for nearly all of AMDs microprocessors as well as for a rich ecosystem of other microprocessors, system controllers, graphics processors, network processors, and communications semiconductors. It is a high-speed, low latency, point-to-point, packetized link. The latest version, HyperTransport 3.1, enables data transfer at rates of up to 51.2 GigaBytes per second. It is scalable, error tolerant, and designed for ease of use. It is also compatible with PCIe, PCI-X, PCI, and AGP buses and includes comprehensive power management and x86 platform support. The HTX and HTX3 specifications define a PC architecture I/O slot that provides the lowest latency slot access to a microprocessor available.Physical signals
I/O Ordering Rules
Error detection and error handling
System management messaging and protocols
Power management messaging and protocols
Packet routing algorithms including fairness
Electrical interface power and signaling
Signal equalization and phase alignment
Channel specification and modeling
HyperTransport bridging and switching
PCIe, PCI-X, PCI, AGP and x86 compatibility
MindShare's HyperTransport 3.1 Interconnect Technology provides a comprehensive guide to all of the releases of HyperTransport technology, from 1.03, through 2.0, to 3.1. This book includes over 250 drawings and over 100 tables.
Additional topics covered include:
The HTX and HTX3 slots
Server platform design
A history of HyperTransport
Terminology through a detailed glossary
MindShare's Technology Series is a crisply written and comprehensive set of guides to the most important computer hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.
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Publisher: MindShare, Inc.
Page Count (est.): 690
Pub Date: 9/17/2008